1. Field of the Invention
The present invention relates to digital level shifters and more particularly, to CMOS low power level shifters.
2. Description of the Prior Art
Integrated circuits such as EPROMs, or erasable programable read-only memories, are often fabricated using complementary metal-oxide semiconductor (CMOS) technology, since very low power dissipation can be achieved. Other fabrication techniques, such as p-channel MOS (PMOS), n-channel MOS (NMOS) or bipolar technologies, can consume orders of magnitude more power than comparable CMOS devices.
In an EPROM device, a relatively high voltage (on the order of 20 volts) is generally necessary to inject electrons into the floating gate in order to program the device. However, most logic functions are conducted at much lower voltages, typically 5 volts. Thus, a digital level shifter is necessary to shift the 5 volt voltage level (which may correspond to a logical HIGH or "1") to a higher voltage level such as 20 volts, in order to program the EPROM.
A typical prior art digital level shifter is shown in FIG. 1. The circuit includes a complementary pair of transistors, one n-channel and one p-channel, which inverts a digital input signal. The inverted signal is then reinverted by a second complementary transistor pair. The second transistor pair is typically connected to a larger supply voltage in order to provide the increased voltage output. This configuration has the disadvantage that if the state of the signal at the input of the second complementary transistor pair is such that the n-channel transistor is turned on, the p-channel transistor is usually turned on also, as a consequence of typical p-channel transistor threshold voltages. With both transistors of the pair turned on, a current path from the voltage supply to ground is present, resulting in undesirable power consumption.
One of the basic criteria for minimizing the power consumed by a device is that there be no direct current path from the voltage supply to ground when the input signals are not in transition. Because of the characteristics of prior art level shifters, however, power can be dissipated through the second complementary transistor pair even though the input signals remain constant.